![]() ![]() AVC, VC1, VP8 and AV1 are available for decoding. Supported codecs include HEVC 264, 265 (8/10bit), VP9 and JPEG. The SoC also has a 16MB System Level Cache shared by the GPU. The high-performance cores have an unusually large 192 KB of L1 instruction cache and 128 KB of L1 data cache and share a 12 MB L2 cache the energy-efficient cores have a 128 KB L1 instruction cache, 64 KB L1 data cache, and a shared 4 MB L2 cache. Apple claims the energy-efficient cores use one-tenth the power of the high-performance ones. This combination allows power-use optimizations not possible with previous Apple–Intel architecture devices. The M1 has four high-performance "Firestorm" and four energy-efficient "Icestorm" cores, providing a hybrid configuration similar to ARM DynamIQ and Intel's Lakefield and Alder Lake processors.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |